The present invention relates in general to a method for manufacturing a semiconductor device; and, more particularly, to a method for manufacturing a semiconductor device using a plate electrode as a fuse.
For a semiconductor memory device, high capacity DRAM devices are widely available. DRAM is defined into a memory cell region storing data or information as charge, and a peripheral circuit region for data input/output. Basically, a conventional DRAM cell consists of one transistor and one capacitor. However, reduction in design rule for highly integrated memory devices has made it difficult to ensure the required electrostatic capacity of the capacitor.
As an attempt to resolve this, a three-dimensional structure, such as a cylindrical structure or a concaved structure, was introduced for a capacitor's storage node.
In case of the cylindrical-capacitor storage node, a trench (cavity) where a capacitor's storage node is formed is provided in an oxide film, and a titanium nitride (TiN) film is deposited on the inside of the trench to form a storage node. The storage node oxide film is then removed by a full dip-out process, and a dielectric film and a plate electrode are formed.
Meanwhile, emerging trends in semiconductor devices of a high degree of integration called for an increase in memory capacity and a larger-size chip. Yet the yield of those semiconductor devices is rather low because if one single cell among numerous microcells was detected to have a defect during the manufacture of such a semiconductor device, the entire device was considered defective and had to be discarded or condemned.
Now, a memory has pre-constructed redundancy cells inside to replace cells having a defect caused during the manufacturing process, so that the entire memory can be revived, leading to an increase in the yield of chips.
When a defective memory cell is identified through a test after the completion of a wafer fabrication process, the repair work using those redundancy cells executes, in an internal circuit, a program changing an address of the defective memory cell to an address of a spare cell. Therefore, when an address signal corresponding to a defect line is input, a spare line is selected in replacement of the line having a defective cell.
To repair a defective circuit after completion of manufacturing process of a semiconductor device, an oxide film on an upper part of a fuse line is removed to open a fuse box, and a laser beam is used to blow and cut a fuse. The wiring that is disconnected by the laser beam emission is called a fuse line, and the region around the fuse line is called a fuse box.
FIGS. 1a through 1f are cross-sectional views stepwisely showing a conventional method for manufacturing a semiconductor device.
Referring to FIG. 1a, an interlayer insulating film 23 is formed over a semiconductor substrate 21 arranged for a cell region and a fuse region, and a storage node contact hole 25 exposing the semiconductor substrate 21 is formed by using a storage node contact mask.
The storage node contact hole 25 is filled to form a storage node contact plug 27.
The formation of the storage node contact plug 27 over the semiconductor substrate 21 will now be explained in detail as follows.
First of all, a device isolation film is formed over the semiconductor substrate 21 arranged for a cell region and a fuse region, and a recess gate is formed in a region arranged for a gate (not shown).
A lower insulating layer (not shown) is formed on an entire upper surface. The lower insulating layer is then etched by a lithographic-process using a landing plug contact mask, so that a landing plug contact hole is formed (not shown), exposing the semiconductor substrate 21 in a bit line contact region and in a storage node contact region.
Next, the landing plug contact hole is filled to thus form a landing plug (not shown), and a first interlayer insulating film is formed on an entire upper surface (not shown).
The first interlayer insulating film is etched by a lithographic-process using a bit line contact mask, to form a bit line contact hole (not shown).
The bit line contact hole is filled up with a conductive film to form a bit line contact plug (not shown).
A bit line (not shown) is formed on an upper part of the bit line contact plug, and a second interlayer insulating film covering the bit line 23 is formed.
The second interlayer insulating film and the first interlayer insulating film in the cell region are etched by a lithographic-process using a storage node contact mask, to form a storage node contact hole 25.
The storage node contact hole 25 is filled up with a conductive film to form a storage node contact plug 27.
An etch stop film 29 is formed on an upper part of the interlayer insulating film 23. At this time, the etch stop film is composed of a nitride film.
Next, a first sacrifice oxide film 31, a second sacrifice oxide film 33, a hard mask layer 35, and an anti-reflective film 37 are sequentially formed on an upper part of the etch stop film 29.
A first photoresist (not shown) is formed on an upper part of the anti-reflective film 37. The first photoresist is exposed and developed by a storage node mask (not shown) to form a first photoresist pattern 39.
With the first photoresist pattern 39 as a mask, the anti-reflective film 37, the hard mask layer 35, the second sacrifice oxide film 33, the first sacrifice oxide film 31, and the etch stop film 29 are etched to form a storage node region 41. Next, the first photoresist pattern 39, the anti-reflective film 37, and the hard mask layer 39 are removed (FIG. 1b).
Referring to FIG. 1c, a conductive film 43 is formed on an entire upper surface including a storage node region 41.
At this time, the conductive film 43 has a laminated structure made up of a titanium (Ti) film and a titanium nitride (TiN) film.
Referring to FIG. 1d, a second photoresist (not shown) is formed on an entire upper surface. The second photoresist is planarized until the second sacrifice oxide film 33 is exposed, and a storage node 44 is completed in this way.
Next, the second photoresist is removed, and a capping oxide film 45 is formed on an entire upper surface.
Referring to FIG. 1e, the capping oxide film 45, the second sacrifice oxide film 33, and the first sacrifice oxide film 31 are completely removed by a full dip-out process in presence of a chemical solution.
Next, a dielectric film 47 is formed on an entire surface of the storage node 44.
Referring to FIG. 1f, a TiN film 49a and a polysilicon film 49b are sequentially laminated on an upper part of the dielectric film 47 to form a plate electrode 49. In this manner, the structure of a capacitor is thus completed.
At this time, the plate electrode 49 in the fuse region is used as a fuse.
Later, a fourth interlayer insulating film (not shown), a first metal wire contact plug (not shown), a first metal wire (not shown), a fifth interlayer insulating film (not shown), a second metal wire contact plug (not shown), a second metal wire (not shown), and a protective film (not shown) are stacked on an upper part of the plate electrode 49.
A fuse open region (not shown) is formed by lithographic-process using a fuse open mask (not shown). The fourth interlayer insulating film of a designated thickness is the only thing remaining on an upper part of the plate electrode 49 in the fuse region.
Next, the plate electrode 49 in the fuse region corresponding to a defective cell is cut by a laser beam (this is a fuse blowing process).
FIGS. 2a and 2b are photos illustrating problems in a method for manufacturing a semiconductor device according to the prior art.
Referring to the photos, a large step height is formed between the plate electrodes 49 in a cell region and in a fuse region because the capping oxide film 45, the second sacrifice oxide film 33, and the first sacrifice oxide film 31 are completely removed during a full dip-out process. The fourth interlayer insulating film is thickly formed on an upper part of the plate electrode 49.
Due to the shortness height of an existing etching target, the fourth interlayer insulating film on an upper part of the plate electrode 49 may not be removed sufficiently but is formed at a thickness greater than its target thickness (about 2500 Å).
That is, the fourth interlayer insulating film having a thickness of about 12500 Å is formed in the fuse box edge section, while the fourth interlayer insulating film having a thickness of about 14000 Å is formed on the inside of the fuse box (FIG. 2b).
In short, according to the related art manufacturing method of a semiconductor device, the fourth interlayer insulating film is formed thickly on an upper part of the plate electrode due to the full dip-out process for forming a cylindrical shaped capacitor, and this causes a shortage of the etching target during the lithographic-process using a fuse open mask.
Consequently, the fourth interlayer insulating film formed on an upper part of the plate electrode has a thickness greater than its target (about 2500 Å). This thick plate electrode is not easily cut by laser blowing, but causes defects.